About Us > Faculty & Staff > Technical Staff > Harlan Stamper Senior RIE and FEP Development Engineer

Professional Background:

• Senior FEOL, MEOL & BEOL RIE Development Engineer, Tokyo Electron Limited, University at Albany and Fishkill, NY
• Process and Quality Engineering Manager, MIC Technology an Aeroflex Company, Pearl River, NY 
• Program Manager / Technical Specialist, MIC Technology an Aeroflex Company, Pearl River, NY
• Senior Process Engineer, MIC Technology an Aeroflex Company, Pearl River, NY
• Lead Process Engineer, Lucent Technologies, Andover, MA
• Process Engineer, Photocircuits Corporation, Glen Cove, NY

Education:

• B.S. Mechanical Engineering, Binghamton University

Responsibilities:

As a Development Engineer, Mr. Stamper is responsible for multiple development activities for planar and non-planar integrations and joint development activities with ASML, Tokyo Electron, Applied Materials, Sematech, IBM and other alliance partners for advanced processing within CNSE's 300mm full-flow wafer processing facility. Mr. Stamper is a key RIE interface point of contact and drives the resolution on RIE related questions and problems.

Mr. Stamper is the Primary Investigator for a number of other projects at CNSE.

Patents:

Forming a dual damascene structure, #US20080241763

Method of etching using a multilayer mask, #US20080292973

Method of forming a dual damascene structure utilizing a developable anti-reflective coating, #7432191

Professional Memberships:

• American Society of Mechanical Engineers
• Pi Tau Sigma Member

Recent Publications and Presentations:

• "Enhanced Performance in SOI FinFETs with Low Series Resistance by Aluminum Implant as a Solution Beyond 22nm Node", I. Ok, C. D. Young, W. Y. Loh, T. Ngai, S Lian, J. Oh, M. P. Rodgers1, S. Bennett1, H. O. Stamper1, D. L. Franca1, S. Lin2, K. Akarvardar3, C. Smith, C. Hobbs, P. Kirsch, R. Jammy
• "Gate-all-around Nanowire FET, (GAA NWFET)", February 2010